CPU clock throttling is described in U.S. Pat. No. 5,546,568. A first time interval during which a CPU operates at a predetermined frequency and a second time interval during which the CPU does not operate at all are alternately provided. The predetermined frequency is multiplied by the ratio of the first time interval to the sum of the two time intervals to obtain the substantial frequency of the CPU. For example, when a predetermined frequency is 100 MHz and the second time interval is 7 while the first time interval is 1, the substantial frequency is 12.5 MHz. The technique of CPU clock throttling is actually employed in a Pentium processor (trademark of Intel Corp.), which is a CPU produced by Intel Corp.
APM (Advanced Power Management) is employed as power management software. APM executes code for processing a power event by employing a special processor mode called a system management mode. The normal state, the standby state, the suspend state and the OFF state are defined by APM, and when a specific event occurs, the mode is shifted to an appropriate mode. An APM driver performs processing concerning the transition of the state and the system maintenance for state transition. For a detailed explanation, see Advanced Power Management (APM) BIOS Interface Specification Revision 1.2, Feb. 1996, Intel Corporation and Microsoft Corporation. Even software conforming to the provisions of APM tends to occupy a CPU for a predetermined period of time, regardless of whether or not there is a job to be executed. For example, even in an operating system, such as Windows 95 (Trademark of Microsoft Corp.), which conforms to the APM provisions, a device driver for a hard disk drive occupies the CPU during a wait period. Therefore, effective power management can not be performed by using only APM.
Japanese Unexamined Patent Publication No. Hei 3-296119 discloses an apparatus that comprises: detection means for detecting an access to an input/output device by a central processing unit; counting means for counting frequencies or the cycle of the access; and switching means for, in accordance with a result obtained by the counting means, switching at least one of the central processing unit and the accessed input/output device from an operational state to a low power consumption state. This publication describes an example wherein the number of times software accesses a keyboard buffer during a predetermined period is counted, and when an access count reaches a specified number, the CPU is halted; and an example wherein it is checked whether the CPU has accessed a VRAM to which display data for a display system is to be written, and when the VRAM has not been accessed within a specified period following the last recorded access, the display controller is halted and a display is erased and shifted to the low power consumption state.
Japanese Unexamined Patent Publication No. Hei 2-244312 discloses a portable information processor with low power consumption that includes communication means, and that normally halts the clock of as internally mounted CPU to initiate low power consumption and permits oscillation of the clock only when its operation is required. In this processor, a DMA function and a function for identifying the head and the end of a transfer block are provided for a circuit, and to consume less power, the clock of the CPU is halted even while communication is in progress.
Japanese Unexamined Patent Publication No. Hei 4-238517 discloses a control method whereby a power controller for powering peripheral hardware monitors an interval of an input/output to the peripheral hardware and an input/output count during a specific unit of time, and controls the power on or off of the peripheral hardware in accordance with the obtained results, so that battery power consumption is reduced as much as possible. In this embodiment, the power controller monitors, for a specific unit of time, an input/output count to a peripheral hardware. When the input/output count during the specific unit of time is less than the previous count, the non-communication monitoring period is extended. When the input/output count is greater, the non-communication monitoring period is shortened. When the non-communication monitoring period has ended following a specified input/output process and then a following input/output process is not performed, the power controller powers off the peripheral hardware.
Japanese Unexamined Patent Publication No. Hei 4-195316 discloses a technique wherein by monitoring a signal between a CPU and a device, an access detector detects the device being operated, that is, an access to the device by the CPU, then outputs an instruction signal to a controller in accordance with the detection to start providing power to the device or providing a clock signal to the device. This publication also describes the access detector that detects the reading by the CPU to one or more specific areas in a memory and outputs a signal for each specific area.
Japanese Unexamined Patent Publication No. Hei 5-11897 discloses a technique for setting a fast clock frequency for a specified period only when an I/O access operation occurs for which a fast clock is required.
Japanese Unexamined Patent Publication No. Hei 8-83133 discloses a technique whereby, when a CPU is to access a relatively slow I/O unit, such as a magneto optical disk drive, the CPU outputs an access request (IORQ) to an I/O controller, and during a predetermined period following the receipt of the IORQ, the I/O controller outputs a WAIT signal instructing the CPU to wait. This predetermined period is set in accordance with the response time from the I/O unit.
In addition, when a specific product sold on the market was examined, it was found that this product employs a method for raising the substantial frequency of a CPU for a specified period, such as several seconds following the issuance of a command to a hard disk, or 4 ms to 8 ms following the occurrence of an event, such as an interrupt from the hard disk. AS the result of the actual power consumed, when this method was employed for Windows95 (trademark of Microsoft Corp.) the following problems were noted. (1) The CPU was maintained in an accelerated state even while it was waiting for a response from the hard disk, and during this period a certain percentage of the total power consumed was wasted. (2) Windows95 adopts a time slice of 13.7 ms as a switching timing of a thread along which a hardware timer periodically issues an interrupt to a schedular in an operating system. Therefore, since, in an apparatus that employs a method for operating a CPU at a high speed for 8 ms for each interrupt, the CPU was operated at a high speed for 8 ms at the interval of 13.7 ms, the CPU was operated at a high speed almost all the time.
A method for resolving only the above problems may be provided by the above described background art; however, in the background art no method is provided whereby power management is balanced by usability.
It is, therefore, one object of the present invention to provide a power management method whereby power saving is balanced by useability.